OMAP GPMC Clock Issue

NOTE: This entry is used as a reference to my TI E2E Discussion.

Update: Fixed. OMAP Register Settings are correct. But Logic Analyser voltage level threshold was wrongly set to TTL. Due to this, signals are sampled wrong points and showed like glitch. The correct threshold  level is LVCMOS.

I am seeing some activity in the GPMC clock pin. But it is no way near to the GPMC clock diagram in TRM. Where the things are going wrong? Here is the Logic Analyser capture:

Gpmc-clk-1-30-03-2011Gpmc-clk-2-30-03-2011Gpmc-clk-3-30-03-2011

Advertisements
Tagged with: ,
Posted in Uncategorized

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out / Change )

Twitter picture

You are commenting using your Twitter account. Log Out / Change )

Facebook photo

You are commenting using your Facebook account. Log Out / Change )

Google+ photo

You are commenting using your Google+ account. Log Out / Change )

Connecting to %s

%d bloggers like this: