NOTE: This entry is used as a reference to my TI E2E Discussion.
Update: Fixed. OMAP Register Settings are correct. But Logic Analyser voltage level threshold was wrongly set to TTL. Due to this, signals are sampled wrong points and showed like glitch. The correct threshold level is LVCMOS.
I am seeing some activity in the GPMC clock pin. But it is no way near to the GPMC clock diagram in TRM. Where the things are going wrong? Here is the Logic Analyser capture: